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LTC1590 Dual Serial 12-Bit Multiplying DAC
FEATURES
s s s s s s s s
DESCRIPTION
The LTC(R)1590 is a dual, serial input 12-bit multiplying digital-to-analog converter (DAC). It includes two current output multiplying CMOS DACs and an easy SPI compatible serial interface with daisy-chain output. An asynchronous CLR pin sets both DACs to zero scale. Excellent accuracy, stability and versatility are combined with the smallest package available for a dual 12-bit multiplying DAC. Parts are available in 16-pin PDIP and narrow SO packages and are specified over the commercial and industrial temperature ranges.
, LTC and LT are registered trademarks of Linear Technology Corporation.
DNL and INL Over Temperature: 0.5LSB Max Gain Error: 1LSB Max Low Supply Current: 10A Max 4-Quadrant Multiplication Power-On Reset Asynchronous Clear Input Daisy-Chain 3-Wire Serial Interface 16-Pin Narrow SO and PDIP Packages
APPLICATIONS
s s s s
Process Control and Industrial Automation Software Controlled Gain Adjustment Digitally Controlled Filter and Power Supplies Automatic Test Equipment
TYPICAL APPLICATION
1.0
Dual 12-Bit 2-Quadrant Multiplying DAC
5V 16 VCC 13 DIN 14 CLK P 24-BIT SHIFT REG AND LATCH VREF B RFB B DAC B OUT2 B 4 11 CS/LD OUT1 B 3
INL (LSB)
VIN A 10V 9
VIN B 10V 1 2 33pF 15V LT (R)1112
Daisy-Chained Control Outputs
- +
VOUT B 10V
8 VREF A RFB A DAC A OUT2 A 5 33pF OUT1 A 6
- +
VOUT A 10V
12 DOUT CLR 15 5V DGND 10 AGND 7 LTC1590 -15V
LTC1590 * TA01
INL (LSB)
U
U
U
Integral Nonlinearity Over Temperature DAC A
THREE SUPERIMPOSED CURVES TA = -40C, 25C, 85C
0.5
0
-0.5
-1.0 0 512 1024 1536 2048 2560 3072 3584 4095 DIGITAL INPUT CODE LTC1590 * TA02
Integral Nonlinearity Over Temperature DAC B
1.0 THREE SUPERIMPOSED CURVES TA = -40C, 25C, 85C
0.5
0
-0.5
-1.0 0 512 1024 1536 2048 2560 3072 3584 4095 DIGITAL INPUT CODE LTC1590 * TA03
1
LTC1590 ABSOLUTE MAXIMUM RATINGS
VCC to AGND ............................................... - 0.5V to 7V VCC to DGND .............................................. - 0.5V to 7V AGND to DGND ............................................. VCC + 0.5V DGND to AGND ..............................................VCC + 0.5V VREF to AGND ........................................................ 25V RFB to AGND .......................................................... 25V Digital Inputs to DGND ................... - 0.5V to VCC + 0.5V VOUT1, VOUT2 to AGND .................... - 0.5V to VCC + 0.5V Maximum Junction Temperature .......................... 150C Operating Temperature Range LTC1590C................................................ 0C to 70C LTC1590I ............................................ - 40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
PACKAGE/ORDER I FOR ATIO
TOP VIEW VREF B 1 RFB B 2 OUT1 B 3 OUT2 B 4 OUT2 A 5 OUT1 A 6 AGND 7 RFB A 8 N PACKAGE 16-LEAD PDIP 16 VCC 15 CLR 14 CLK 13 DIN 12 DOUT 11 CS/LD 10 DGND 9 VREF A
ORDER PART NUMBER LTC1590CN LTC1590CS LTC1590IN LTC1590IS
S PACKAGE 16-LEAD PLASTIC SO
TJMAX = 150C, JA = 100C/W (N) TJMAX = 150C, JA = 150C/W (S)
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
VCC = 4.5V to 5.5V, VREF = 10V, VOUT1 = VOUT2 = AGND = DGND = 0V, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL Accuracy Resolution INL DNL GE Integral Nonlinearity Differential Nonlinearity Gain Error Gain Temperature Coefficient ILEAKAGE OUT1 A, OUT1 B Leakage Current Zero-Scale Error PSRR RREF Power Supply Rejection VREF Input Resistance VREFA, VREFB Input Resistance Match AC Performance (Note 3) Digital-to-Analog Glitch Impulse Multiplying Feedthrough Error Output Current Settling Time Channel-to-Channel Isolation Digital Crosstalk Output Noise Voltage Density THD Total Harmonic Distortion Multiplying Bandwidth (Notes 5, 6) (Note 11) (Note 5) To 0.01% for Full-Scale Change (Note 7) (Notes 5, 8) (Note 9) (Note 10) (Note 12) 1 13 - 108 1 - 92 1 - 89 0.3 - 80 0.8 - 90 nV-s dB s dB nV-s nV/Hz dB MHz (Note 1) Guaranteed Monotonic, TMIN to TMAX (Note 2), TA = 25C TMIN to TMAX (Note 3) Gain/Temperature (Note 4), TA = 25C TMIN to TMAX TA = 25C TMIN to TMAX VCC = 5V 10%
q q q q q q q q
PARAMETER
CONDITIONS
MIN 12
TYP
MAX
UNITS Bits
0.5 0.5 1 2 1 5 5 25 0.03 0.15 0.0001 8 11 0.002 15 3
ppm/C nA nA LSB LSB %/% k %
Reference Input
q q
2
U
LSB LSB LSB LSB
W
U
U
WW
W
LTC1590
ELECTRICAL CHARACTERISTICS
VCC = 4.5V to 5.5V, VREF = 10V, VOUT1 = VOUT2 = AGND = DGND = 0V, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL COUT PARAMETER Output Capacitance (Note 3) CONDITIONS DAC Register Loaded to All 1s DAC Register Loaded to All 0s
q q
MIN
TYP 60 30
MAX 90 60
UNITS pF pF V
Analog Outputs
Digital Input VIH VIL IIN CIN VOH VOL t1 t2 t3 t4 t5 t6 t7 t8 t9 VCC ICC Digital Input High Voltage Digital Input Low Voltage Digital Input Current Digital Input Capacitance Digital Output High Voltage Digital Output Low Voltage DIN to CLK Setup Time DIN to CLK Setup Hold Time CLK High Time CLK Low Time CS/LD High Time LSB CLK to CS/LD CS/LD Low to CLK High CLK Low to CS/LD Low CLK to DOUT Delay Operating Supply Range Supply Current Digital Inputs = 0V or VCC (Note 3) VIN = 0V IOH = 200A IOH = 1.6mA
q q q q
2.4 0.8 0.001 1 8 4 0.4 50 0 40 40 50 40 20 20 10 4.5 5 160 5.5 10
V A pF V V ns ns ns ns ns ns ns ns ns V A
Digital Output
q q
Timing Characteristics
q q q q q q q q q
Power Supply
q q
The q denotes specifications which apply over the full operating temperature range. Note 1: 0.5LSB = 0.012% of full scale. Note 2: Using internal feedback resistor. Note 3: Guaranteed by design, not subject to test. Note 4: IOUT1 with DAC register loaded with all 0s. Note 5: OUT1 load = 100 in parallel with 13pF. Note 6: VREF = 0V. DAC register contents changed from all 0s to all 1s or all 1s to all 0s. Note 7: DAC A output with VREF A = 0V and VREF B = 10kHz 20VP-P, or DAC B output with VREF B = 0V, VREF A = 10kHz 20VP-P. Both DAC registers loaded with all 1s.
Note 8: Glitch on DAC A or DAC B output when the other DAC makes a full-scale transition. Note 9: 10Hz to 100kHz. Calculation from en = 4KTRB where: K = Boltzmann constant (J/K); R = resistance (); T = resistor temperature (K); B = bandwidth (Hz). Note10: VREF = 6VRMS at 1kHz. DAC register loaded with all 1s, using LT (R)1124 op amp. Note 11: VREF = 10V, 10kHz sine wave, DAC register loaded with all 0s, using LT1358 op amp. Note 12: -3dB bandwidth using LT1358 op amp.
3
LTC1590 TYPICAL PERFORMANCE CHARACTERISTICS
Full-Scale Settling Waveform
VDD = 5V 0V TO 5V OUTPUT RANGE LT1363 OP AMP CFB 30pF
1.0
0.5
DIFFERENTIAL NONLINEARITY (LSB)
512 1024 1536 2048 2560 3072 3584 4095 DIGITAL INPUT CODE
1590 G02
INTEGRAL NONLINEARITY (LSB)
OUTPUT VOLTAGE (1V/DIV)
TIME (500ns/DIV)
1590 G12
Multiplying Mode Signal-to(Noise + Distortion) vs Frequency
-50 SIGNAL-TO-(NOISE + DISTORTION) (dB) VDD = 5V -60 -70 -80 -90 -100 USING AN LT1007 WITH 22kHz FILTER -110 1 10 FREQUENCY (kHz) 50
1590 G10
DIFFERENTIAL NONLINEARITY (LSB)
INTEGRAL NONLINEARITY (LSB)
USING AN LT1363 WITH 500kHz FILTER
Multiplying Mode Frequency Response vs Digital Code
0 10 20
ATTENUATION (dB)
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 VREF = 2V VREF = 10V
DIFFERENTIAL NONLINEARITY (LSB)
INTEGRAL NONLINEARITY (LSB)
30 40 50 60 70 80 90
ALL BITS OFF
100 100
1k
100k 10k FREQUENCY (Hz)
4
UW
1M
1590 G07
Integral Nonlinearity (INL)
1.0
Differential Nonlinearity (DNL)
0.5
0
0
-0.5
-0.5
-1.0 0
-1.0 0 512 1024 1536 2048 2560 3072 3584 4095 DIGITAL INPUT CODE
1590 G03
Integral Nonlinearity vs Reference Voltage
0.20 VDD = 5V 0.15
0.20
Differential Nonlinearity vs Reference Voltage
VDD = 5V 0.15
0.10
0.10
0.05
0.05
0
0
2
3
6 8 5 7 4 REFERENCE VOLTAGE (V)
9
10
2
3
4 5 6 7 8 REFERENCE VOLTAGE (V)
9
10
1590 G05
1590 G06
Integral Nonlinearity vs Supply Voltage
ALL BITS ON 1.0 0.9 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 9 10
Differential Nonlinearity vs Supply Voltage
VREF = 2V VREF = 10V
10M
0
2
3
4
5 6 7 8 SUPPLY VOLTAGE (V)
2
3
4
5 6 7 8 SUPPLY VOLTAGE (V)
9
10
1590 G08
1590 G09
LTC1590 TYPICAL PERFORMANCE CHARACTERISTICS
Midscale Glitch Impulse
4
VDD = 5V LT1363 OP AMP CFB = 30pF
LOGIC THRESHOLD (V)
OUTPUT VOLTAGE (50mV/DIV)
2
SUPPLY CURRENT (mA)
0 5 10 SUPPLY VOLTAGE (V) 15
1590 G04
TIME (500ns/DIV)
1590 G11
PIN FUNCTIONS
VREF B, VREF A (Pins 1, 9): Reference Inputs for DAC A/B. Typically 10V, accepts up to 25V. RFB B, RFB A (Pins 2, 8): Feedback Resistors for DAC A/B. Normally tied to the output of current to voltage converter op amp. Typically swings to 10V. Swings from 0V to - VREF. OUT1 B, OUT1 A (Pins 3, 6): True Current Output for DAC A/B. Normally tied to inverting input of current to voltage converter op amp. OUT2 B, OUT2 A (Pins 4, 5): Complement Current Output for DAC A/B. Normally tied to ground. AGND (Pin 7): Analog Ground Pin. Tie to ground. DGND (Pin 10): Digital Ground Pin. Tie to ground. CS/LD (Pin 11): The Serial Interface Enable and Load Control Input. When CS/LD is low the CLK signal is enabled so the data can be clocked in. When CS/LD is pulled high, data is loaded from the shift register into the DAC register, updating the DAC output. DOUT (Pin 12): The Serial Data Output. Data becomes valid on the rising edge of the CLK. DIN (Pin 13): The Serial Data Input. Data on the DIN pin is latched into the shift register on the rising edge of the serial clock. Data is loaded as one 24-bit word. The first 12 bits are for DAC A, MSB-first and the second 12 bits are for DAC B, MSB-first. CLK (Pin 14): The Serial Interface Clock Input. CLR (Pin 15): The Clear Pin for the DAC. Clears both DACs to zero scale when pulled low. This pin should be tied to VCC for normal operation. VCC (Pin 16): The Positive Supply Input. 4.5 VCC 5.5V. Requires a bypass capacitor to ground.
UW
Logic Threshold vs Supply Voltage
1.0
3
Supply Current vs Logic Input Voltage
0.5
1
0
0 0
1
3 2 INPUT VOLTAGE (V)
4
5
1590 G01
U
U
U
5
LTC1590
BLOCK DIAGRA
VREF B
1 40k 40k 40k 40k 40k 40k 40k 10k
VREF A
9 DAC A
CS/LD 11
CLK 14 DIN 13
TIMING DIAGRAMS
OPERATING SEQUENCE
DAC A INPUT MSB DIN D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB MSB D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DAC B INPUT LSB D0
CLK
1
2
3
4
5
CS/LD (ENABLE CLOCK) (UPDATE DAC OUTPUT)
LTC1590 * TD
6
W
W
20k 20k 20k 2 RFB B 3 OUT1 B 4 OUT2 B DECODER DAC B D10 D9 DAC REGISTER B D8 D0 (LSB) D11 (MSB) LOAD 12 8 RFB A 6 OUT1 A 5 OUT2 A 12 CLK IN 16 VCC 10 DGND 7 AGND INPUT 24-BIT SHIFT REGISTER OUT 12 DOUT
1590 * BD
UW
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
LTC1590
TIMING DIAGRAMS
TIMING DIAGRAM
t8 CLK t7 1 t1 t2 3 2 t4 t3 23 24 t6
DIN
CS/LD
DOUT
D11 A PREVIOUS WORD
APPLICATIONS INFORMATION
Description The LTC1590 is a dual 12-bit multiplying DAC that has serial inputs and current outputs. It uses precision R/2R resistor ladder technology to provide exceptional linearity and stability. The device operates from a single 5V supply and provides a 10V reference input and voltage output range when used with an external op amp. Serial I/O The LTC1590 has a 3-wire SPI/MICROWIRETM compatible serial port that accepts 24-bit serial words. Data is loaded MSB first with the first 12 bits controlling DAC A and the second 12 bits controlling DAC B. Data is shifted into the DIN input on the rising edge of CLK. The CS/LD input must be taken low before transferring data to enable the CLK input. After transferring data, CS/LD is pulled high to load data from the shift register to the DAC registers which updates both DACs. The buffered output of the 24-bit shift register is available on the DOUT pin. Multiple DACs can be daisy-chained on one 3-wire interface by connecting the DOUT pin to the DIN pin of the next DAC (see the Timing Diagrams section).
MICROWIRE is a trademark of National Semiconductor Corporation.
U
W
W
U
U
UW
D11 A MSB
D10 A
D9 A
D1 B
D0 B LSB
t5
t9 D10 A PREVIOUS WORD D9 A PREVIOUS WORD D0 B PREVIOUS WORD D11 A CURRENT WORD
1590 TD02
Equivalent Circuit Figure 1 shows an equivalent analog circuit for the LTC1590 DACs. R is the reference input, RREF, which is nominally 11k. The DAC output is represented by the Thevinin equivalent current source with a value of: (Code/4096)(VREF/R) The current source ILKG models the junction leakage of the DAC output switches. ILKG is typically less than 5nA at 85C and decreases by roughly two times for every 10C reduction in temperature. COUT is the output capacitance, and it also comes from the DAC output switches and varies from 30pF at zero scale to 60pF at full scale. RO is the equivalent output resistance, which varies with digital input code (see Op Amp Selection section).
R VREF A VREF B R RFB A RFB B OUT1 A OUT1 B COUT OUT2 A OUT2 B AGND
1590 F01
( )( )
CODE VREF 4096 R
ILKG RO
Figure 1. Equivalent Circuit
7
LTC1590
APPLICATIONS INFORMATION
Unipolar 2-Quadrant Multiplying Mode (VOUT = 0V to - VREF) The LTC1590 can be used with a dual op amp to provide a dual 2-quadrant multiplying DAC as shown in Figure 2. The unipolar DAC transfer function is shown in Table 1. The 33pF feedback capacitor is recommended to compensate for the pole caused by the internal feedback resistor and the OUT1 output capacitance. For high speed op amps this feedback capacitor is required for stability, and a smaller value, 8pF to 15pF, may be desired to get the fastest transient response and shortest settling time. A larger feedback capacitor can be used to reduce wideband noise, glitch impulse and distortion for lower frequency signals. A pole is introduced in the DAC transfer function at approximately (CFB)(RFB). For example, a 100pF feedback capacitor will typically give a pole at:
Table 1. Unipolar Binary Code Table
DIGITAL INPUT BINARY NUMBER IN DAC REGISTER MSB 1111 1000 0000 0000 1111 0000 0000 0000 LSB 1111 0000 0001 0000 - VREF (4095/4096) - VREF (2048/4096) = - VREF/2 - VREF (1/4096) 0V ANALOG OUTPUT VOUT
145kHz =
2 100pF 11k
(
1
)(
)
15V
5V 0.1F VCC
VREF -10V TO 10V 33pF
Figure 2. Unipolar Operation (2-Quadrant Multiplication)
R2 20k R3 20k
VREF -10V TO 10V 5V 0.1F VCC VREF RFB OUT1
OUT2 DGND AGND
-15V
Figure 3. Bipolar Operation (4-Quadrant Multiplication)
8
+
-
LTC1590 DAC A OR DAC B
+
-
+
LTC1590 DAC A OR DAC B OUT2 DGND AGND
-
VREF
RFB OUT1
1/2 LT1112
-15V
U
W
U
U
Bipolar 4-Quadrant Multiplying Mode (VOUT = - VREF to +VREF) The circuit of Figure 3 can be used to provide a dual 4-quadrant multiplying DAC. This circuit starts with the unipolar application circuit and adds three resistors and an op amp. These extra devices provide a gain of - 2 from the unipolar output to the bipolar output, plus an offset of (-1)(VREF) to produce the transfer function shown in Table 2. A pack of matched 20k resistors, with two resistors in parallel forming the 10k resistor, is recommended.
Table 2. Bipolar Offset Binary Code Table
DIGITAL INPUT BINARY NUMBER IN DAC REGISTER MSB LSB 1111 0000 0000 1111 0000 1111 0001 0000 1111 0000 +VREF (2047/2048) +VREF (1/2048) 0V - VREF (1/2048) - VREF (2048/2048) = - VREF ANALOG OUTPUT VOUT
VOUT 0V TO -VREF
1590 F02
1111 1000 1000 0111 0000
33pF
15V R1 10k 15V
1/2 LT1112
1/2 LT1112
VOUT -VREF TO VREF
-15V
1590 F03
LTC1590
APPLICATIONS INFORMATION
Op Amp Selection To maintain the excellent accuracy and stability of the LTC1590 thought should be given to op amp selection. Fortunately, the sensitivity of INL and DNL to op amp offset has been significantly reduced compared to competing parts of this type. The op amp's VOS causes DAC output offset. In addition, because the DAC's equivalent output resistance RO changes as a function of code, there is a code-dependent DAC output error proportional to VOS. For fixed reference applications this causes gain, INL and DNL error. For multiplying applications, a code-dependent, DC output voltage error is seen. At zero scale the DAC output error is equal to the op amp offset, and at full scale the output error is equal to twice the op amp offset. For example, a 1mV op amp offset will cause a 0.41LSB zeroscale error and a 0.82LSB full-scale error with a 10V fullscale range. The offset caused INL error is approximately 0.4 times the op amp VOS and DNL error is 0.07 times op amp VOS. For the same example of 1mV op amp VOS and 10V full-scale range, the INL degradation will be 0.17LSB and DNL degradation will be 0.03LSB. Op amp bias current causes only an offset error equal to (IBIAS)(RFB) (IBIAS)(11k). For example, a 100nA op amp bias current causes a 1.1mV DAC offset, or 0.45LSB for a 10V full-scale range. It is important to note that connecting the op amp noninverting input to ground through a resistor will not cancel bias current errors and should never be done! Similarly an offset caused by op amp bias current should not be adjusted by using the op amp null pins since this increases offset between DAC OUT1 and OUT2 pins, causing INL, DNL and gain errors. If op amp offset error adjustment is required, the op amp input offset voltage (the voltage difference between OUT1 and OUT2) should be nulled. Grounding As with any high precision data converter, clean grounding is important. A low impedance analog ground plane and star grounding should be used. OUT2 carries the complementary DAC output current and should be tied to the star ground with as low a resistance as possible. Other ground points that must be tied to the star ground point include the VREF input ground, the op amp noninverting input(s) and the VOUT ground reference point.
TYPICAL APPLICATIONS
Dual Programmable Attenuator
5V VIN B 10V 15V 16 1 VREF B 2 33pF 13 DIN 14 CLK 11 CS/LD 12 DOUT 15 CLR 24-BIT SHIFT REG AND LATCH RFB B DAC B OUT2 B 4 3 0.01F OUT1 B 3 2
0.1F
DATA IN SERIAL CLOCK CHIP SELECT/DAC LOAD DATA OUT CLEAR
7 10
AGND DGND
VREF A 9 VIN A 10V
U
W
U
U
U
- +
8 1/2 LT1358 1 VOUT B
LTC1590 OUT2 A 5 DAC A OUT1 A 6 RFB A 33pF 8 -15V 6 5
VOUT = -VIN
()
D 4096 VOUT A
+
1/2 LT1358 7
-
4 0.01F
1590 TA07
9
LTC1590
TYPICAL APPLICATIONS
Very Low Power Single Supply Dual VOUT DAC
500k 50k
50k V+ 3.3V 16 VCC RFB B DAC B 0.2V 120k 8 LT1004-1.2 210k LTC1590 RFB A DAC A 5 OUT2 A ISUPPLY TOTAL = 100A (TYP) (WORSE-CASE CODE) VREF A 4 OUT2 B 1 9
2 V+ 3.3V
3 OUT1 B
VREF B
1/4 LT1179
6 OUT1 A
0.1F
50k AGND 7 DGND 10
Dual Programmable Gain Amplifier
VIN B 10V
5V
0.1F
15V 16 1 VREF B 2 33pF RFB B DAC B OUT2 B 4 24-BIT SHIFT REG AND LATCH 3 0.01F OUT1 B 3 2
DATA IN SERIAL CLOCK CHIP SELECT/DAC LOAD DATA OUT CLEAR
13 DIN 14 CLK 11 CS/LD 12 DOUT 15 CLR
- +
8 1/2 LT1358 1 VOUT B
LTC1590 OUT2 A 5 DAC A 5
+
1/2 LT1358 7 VOUT A
7 10
OUT1 A 6 AGND DGND 9 8 VIN A 10V VREF A RFB A 33pF
6
-
4 0.01F -15V
1590 TA08
10
+
+
-
-
U
1/4 LT1179
VOUT A
500k
1/4 LT1179
VOUT B 0V TO 2.2V
+
-
1590 TA06
VOUT = -VIN
()
4096 D
LTC1590
TYPICAL APPLICATIONS
Dual Programmable Gain Amplifier with Input Attenuation
VIN B 10V 1k 5V 1k 0.1F 16 1 VREF B 2 RFB B DAC B OUT2 B 4 24-BIT SHIFT REG AND LATCH 3 15k 15k 15V 33pF 0.01F OUT1 B 3 2
DATA IN SERIAL CLOCK CHIP SELECT/DAC LOAD DATA OUT CLEAR
13 DIN 14 CLK 11 CS/LD 12 DOUT 15 CLR
7 10
AGND DGND 1k
PACKAGE DESCRIPTION
0.300 - 0.325 (7.620 - 8.255)
0.009 - 0.015 (0.229 - 0.381)
(
+0.025 0.325 -0.015 8.255 +0.635 -0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
U
- +
8 1/2 LT1358 1 VOUT B
LTC1590 OUT2 A 5 DAC A OUT1 A 6 VREF A 9 RFB A 33pF 8 15k 1k 15k VIN A 10V -15V 6 5
VOUT = -VIN
()
4096 16D VOUT A
+
1/2 LT1358 7
-
4 0.01F
1590 TA09
Dimensions in inches (millimeters) unless otherwise noted. N Package 16-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.770* (19.558) MAX 16 15 14 13 12 11 10 9
0.255 0.015* (6.477 0.381)
1 0.130 0.005 (3.302 0.127) 0.015 (0.381) MIN
2
3
4
5
6
7
8
0.045 - 0.065 (1.143 - 1.651)
0.065 (1.651) TYP 0.125 (3.175) MIN 0.005 (0.127) MIN 0.100 0.010 (2.540 0.254) 0.018 0.003 (0.457 0.076)
N16 0695
)
11
LTC1590
PACKAGE DESCRIPTION
0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254)
0.053 - 0.069 (1.346 - 1.752) 0 - 8 TYP
0.016 - 0.050 0.406 - 1.270
0.014 - 0.019 (0.355 - 0.483)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
TYPICAL APPLICATION
5V
0.1F
16
DATA IN SERIAL CLOCK CHIP SELECT/DAC LOAD DATA OUT CLEAR
13 DIN 14 CLK 11 CS/LD 12 DOUT 15 CLR 24-BIT SHIFT REG AND LATCH
7 10
AGND DGND
RELATED PARTS
PART NUMBER LTC1595 LTC1596 LTC7541A LTC7543/LTC8143 LTC7545A LTC8043 DESCRIPTION 16-Bit Multiplying IOUT DAC in SO-8 16-Bit Multiplying IOUT DAC Parallel I/O Multiplying IOUT 12-Bit DAC Serial I/O Multiplying IOUT 12-Bit DACs Parallel I/O Multiplying IOUT 12-Bit DAC Serial I/O Multiplying IOUT 12-Bit DAC COMMENTS True 16-Bit Upgrade for DAC8043 True 16-Bit Upgrade for DAC8143 and AD7543 12-Bit Wide Parallel Input Clear Pin and Serial Data Output (LTC8143) 12-Bit Wide Latched Parallel Input 8-Pin SO and PDIP
1590f LT/TP 1197 4K * PRINTED IN USA
12
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417q (408)432-1900 FAX: (408) 434-0507q TELEX: 499-3977 q www.linear-tech.com
U
Dimensions in inches (millimeters) unless otherwise noted.
S Package 16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.386 - 0.394* (9.804 - 10.008) 16 0.004 - 0.010 (0.101 - 0.254) 0.228 - 0.244 (5.791 - 6.197) 0.150 - 0.157** (3.810 - 3.988) 15 14 13 12 11 10 9
0.050 (1.270) TYP
1
2
3
4
5
6
7
8
S16 0695
U
Dual Programmable Attenuator with Gain
VIN B 10V
1k
15k 15k 15V 1 2 1k RFB B DAC B OUT2 B 4 3 33pF 0.01F OUT1 B 3 2
VREF B
- +
8 1/2 LT1358 1 VOUT B
LTC1590 OUT2 A 5 DAC A OUT1 A 6 VREF A 9 1k 15k RFB A 1k 8 15k 33pF -15V 6 5
VOUT = -VIN
()
16D 4096 VOUT A
+
1/2 LT1358 7
-
4 0.01F
1590 TA10
VIN A 10V
(c) LINEAR TECHNOLOGY CORPORATION 1997

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